State Reduction Methods for Automatic Formal Verification H Signed I H Signed I H Signed I

Validation of industrial designs is becoming more challenging as technology advances and demand for higher performance increases. One of the most suitable debugging aids is automatic formal veri cation. Unlike simulation, which tests behaviors under a speci c execution, automatic formal veri cation tests behaviors under all possible executions of a system. Therefore, it is able to detect errors that cannot be reliably repeated using simulation. However, automatic formal veri cation is limited by the state explosion problem. The number of states for practical systems is often too large to check exhaustively within the limited time and memory that is available. Existing solutions have widened the range of veri able systems, but they are either insu cient or hard to use. This thesis presents several techniques for reducing the number of states that are examined in automatic formal veri cation. These techniques have been evaluated on high-level descriptions of industrial designs, rather than gate-level descriptions of circuits, because maximum economic advantage of using veri cation relies on catching the most expensive errors as early as possible. A major contribution of this thesis is the design of simple extensions to the Mur' description language, which enable us to convert two existing abstraction strategies into fully automatic algorithms, making these strategies easy to use and safe to apply. The algorithms rely on two facts about high-level designs: they frequently exhibit structural symmetry, and their behavior is often independent of the exact number of replicated components they contain. A static analysis of a Mur' description can identify these characteristics, and the veri cation tool (or the user) can then safely change the description to include appropriate extensions. With the extensions, the